Multi-level memory circuit with regulated writing voltage

ABSTRACT

A multi-level memory circuit for binary information includes a plurality of memory cells each adapted to store more than one item of binary information, and each memory cell includes at least one floating gate MOS transistor. The information stored therein corresponds to the level of the cell threshold voltage. A write signal generating circuit is adapted to an input supply voltage and provides a write voltage to the memory cells. The write signal generating circuit generates internally at least one write voltage having a selectable or selected value from a number of discrete regulated values corresponding to the number of the discrete levels provided.

FIELD OF THE INVENTION

This invention relates to a multi-level type of memory circuit forbinary information.

Memories of this type are usually termed "non-volatile" because of theircapability to retain stored information over very long time periods,even in the absence of a power supply, and include the EPROM, EEPROM,and FLASH EEPROM families.

BACKGROUND OF THE INVENTION

Known own from U.S. Pat. Nos. 5,218,569 and 5,394,362 are multi-levelnon-volatile memories of this type. The construction of a FLASH EEPROMmulti-level memory is also described in an article TA 7.7, "A MultilevelCell 32Mb Flash Memory", ISSCC95 Conference, Feb. 16, 1995.

These publications also address and solve the problem of programming orwriting by a cyclical repetition of program pulses and verificationsteps; specifically, a cell to be written into is applied, between itsgate and source terminals, a voltage write pulse from a row decodingcircuit which is power ed by a supply circuit. The cell is then readfrom to verify the level of its threshold voltage and decide on whethera new pulse is to be applied thereto or the programming brought to anend.

The above article postulates a four-level program and a distribution ofthe threshold voltages of approximately 500 mV for each level. Thisinvolves a spacing of about 500 mV between levels, for a supply voltageof about 3.3 V to the integrated electronic storage device.

If the supply voltage were lower, as is in the wish of so manymanufacturers of electronic apparatus for telecommunicationsapplications, for example, such values would have to be reduced, and bereduced still further as the number of the levels increases.

The provision of distributions so narrow and levels so close togetherrequires extended programming times, because the number of the programcycles has to be increased, as well as highly sophisticated and complexread circuits.

This invention is based on the observation that, when a set ofnon-volatile memory cells having a given distribution of thresholdvoltages are subjected to the same electrical "treatment", thedistribution remains near-constant and shifts in voltage by an amountnot determinable with any great accuracy.

This invention proposes, therefore, of arranging for the writeoperations to be electrically identical for all the cells; this beingaccomplished by so regulating the write voltage as to make itindependent of at least the supply voltage.

To avoid read errors due to shifting inaccuracy, it would be ofadvantage if the levels could be well spaced apart; this being obtainedby generating a high write voltage internally with respect to the supplyvoltage.

With the levels well spaced apart, the write operation is less critical,and can be carried out advantageously with a single pulse of properlyregulated width and duration.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more clearly appreciated from the followingdescription, to be read in conjunction with the accompanying drawings,in which:

FIG. 1 illustrates cell characteristics vs. associated levels and gainvariations;

FIG. 2 illustrates the architectures of a conventional electronicstorage device and one according to the invention;

FIG. 3 shows distributions of cell threshold voltages vs. associatedlevels; and

FIGS. 4 and 5 show first and second circuit diagrams for part of agenerating circuit according to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 depicts an ideal situation in which the cells associated with onelevel have exactly the same threshold voltage. In the instance of FIG.1, there are tour discrete levels DL0, DL1, DL2, DL3 provided which areassociated with four discrete cell threshold voltage values L0, L1, L2,L3. This can only be obtained by adopting extremely complicated writeand erase methods, and such a situation can at best be approached inactual practice.

Irrespective of the method used, the characteristics of the variouscells associated with one level are bound to be different because themanufacture of integrated circuits cannot yield perfectly identicalcells. Thus, such characteristics will show a distribution, as indicatedby dash lines and referenced DL0, DL1, DL2, DL3 in FIG. 1, centeredabout an average characteristic indicated by a full line in FIG. 1. Theparameter that differentiates cells in the same distribution is theso-called "gain" of a cell.

A read operation is to find the intersection of the characteristic of acell to be read from with a read line; FIG. 1 shows three viable readlines RD1, RD2, RD3.

It will be apparent from FIG. 1 that for an "easy" reading, i.e. withbut a slight chance of confusing between levels, the latter should bespaced well apart. FIG. 1 illustrates a typical situation where thesupply voltage VCC is low, e.g. 2.2 volts. It should be understood thatit is not necessary for the level spacings to be uniform as shown inFIG. 1; on the contrary, the spacings can be optimized as mostappropriate for reading.

All three of the read lines RD1, RD2, RD3 require that a cell besupplied a higher voltage VGS than the supply voltage VCC. In addition,the lines RD2 and RD3 require that the value of the voltage VGS becontrolled according to the current ID flowing between the drain andsource terminals of the cell being read from; such lines should bepositioned so that cells associated with different levels can be readilydifferentiated from one another.

An easily implemented read line is the line RD1, which corresponds tothe normal read mode previously described. The read voltage VL should beat least higher than the level L2--the last-but-one from the bottom--forotherwise the levels L2 and L3 cannot be differentiated according to thecurrent ID. Having a higher voltage VL than the level L3 would be oflittle use, and could entail two disadvantages: on the one side, itbecomes necessary to discriminate among four different values of thecurrent ID, and on the other, when moving closer to the top, there wouldbe a risk of confusing the levels, in particular L0 and L1, due to theirdiverging characteristics.

FIG. 3 illustrates the effect of the write method on the thresholdvoltage distributions. Seeing that if a set of cells having a givendistribution are subjected to precisely the same electrical "treatment",the distribution remains near-constant and shifts in voltage, anuncertainty about the extent of the shift will depend substantially onthe write method. By using a fairly simple method, the effect from aninitial level L0 can be that shown in FIG. 3 for different end levelsL1, L2, L3.

The divergence problem in connection with a simple read method--readline RD1--and a simple write method, restricts the number of the levels,and the more so where CMOS technologies are used in which the usablevoltages tend to be limited, e.g. in the range of 12 to 15 volts.

The multi-level memory circuit of this invention comprises:

a) a plurality of memory cells, each adapted to store more than one itemof binary information and comprised of at least one floating gate MOStransistor, the information stored in each cell corresponding to thelevel of the cell threshold voltage; and

b) a write signal generating circuit for the cell plurality, adapted tobe input a supply voltage.

The write signals are electrically the same for all the cells, for agiven information to be stored, they having widths of regulated value.Thus, for example, if each cell is to store an item of binaryinformation corresponding to two bits, four different write signalswould be needed, in theory. Actually, since non-volatile memories cannotbe reprogrammed, three discrete write signals can suffice because thefourth level is obtained by erasing.

Such a memory circuit may require that the generating circuit be adaptedto generate internally a write voltage having a value selectable from anumber, three in this example, of discrete regulated valuescorresponding to the number, four in this example, of the discretelevels provided.

Alternatively, the generating circuit could generate internally anumber, three in this example, of write voltages having discreteregulated values corresponding to the number, four in this example, ofthe discrete levels provided. This alternative would be of advantagewhere several memory cells, possibly in separate arrays, must beprogrammed simultaneously.

One way of generating regulated voltages is to use a linear type ofvoltage regulating circuit provided with a reference circuit forgenerating a stable reference voltage. Where more than one discretewrite voltages are to be generated, a number of regulating circuitswould be required.

In view of that, to generate a plurality of discrete regulated voltages,in a linear regulator, a corresponding plurality of discrete referencevoltages are required, the regulator circuit may be advantageouslyarranged to include a voltage divider connected to the output of thereference circuit and having a plurality of center taps to provide acorresponding plurality of reference voltages. In this way, thereference voltages will be stable as well as tied to one another instable ratii, determinable with great accuracy. The reference voltagesso generated can be coupled selectively to a single regulator by meansof controlled switches, or be coupled to discrete regulators.

To avoid read errors due to shifting inaccuracy, it is advantageous ifthe level spacings are large. This can be accomplished by raising thevoltage internally, where no external voltage source is available with asufficiently high value. In this case, the generating circuit mayinclude a voltage boosting circuit, adapted to output a write voltageexceeding the value of the supply voltage, and at least one voltageregulating circuit connected to the boosting circuit output. Thisrequirement is specially stringent where the circuit is input no programvoltage usually denoted by the reference VPP.

With the levels well spaced apart, the write operation becomes lesscritical. The generating circuit may then be designed to generate asingle write voltage pulse, for each write operation into a cell, whoseamplitude corresponds to one of the regulated discrete write voltagevalues, specifically that associated with the information to be stored.In this case, it is convenient if the generating circuit can alsoregulate the pulse duration accurately; in this way, the write signalswould be electrically identical for the various cells.

When simple read/write methods are chosen, the ideal number of discretelevels is four.

The present circuit is applicable in particular to either EPROMs or OTP(One Time Programmable) memories (OTP memories being basicallynon-erasable EPROMs in that they lack a UV radiation transparentwindow), because the uncertitude in the distribution shift would bethere only once. In fact, reprogramming is impossible, and erasing iseither impossible or effected by a separate physical process. In thiscase, the number of levels can be raised to sixteen at an error ratewhich is still acceptable.

The inventive memory circuit just described can be included in asemiconductor integrated electronic storage device or a genericsemiconductor integrated electronic device in combination with at leastone logic circuit connected to the memory circuit for reading and/orwriting information.

An EPROM semiconductor integrated electronic storage device will now bedescribed by way of example with the aid of FIGS. 2, 4 and 5.

The architecture of FIG. 2 comprises a matrix MTX of memory cellsorganized into rows and columns. Connected thereto are a row decoderRDEC and a column decoder CDEC, which are input row RADR and column CADRaddresses. The decoder CDEC is connected to an input/output managingcircuit IOM which performs physically the read/write operationsfrom/into the cells according to input signals I thereto and outputsignals O therefrom.

The circuits in the architecture of FIG. 2 need to be powered, which isaccomplished by means of a power supply circuit ALIM receiving anexternal supply voltage VCC and external program voltage VPP. Ingeneral, EPROMs are only supplied the voltage VPP during the off-lineprogramming phase. In particular, the circuit ALIM supplies the decoderRDEC with a voltage VW for the word line which may be regarded as theread voltage during read operations, and the write voltage during writeoperations.

The storage devices further require, and do include, a control circuitCNTRL which is supplied the voltage VCC to control the operation of thevarious internal circuits according to input control signals, not shownin FIG. 2.

The circuits shown in FIGS. 4 and 5 illustrate two alternatives for aportion of the circuit ALIM which is utilized to generate the read orwrite voltage VW, as the case may be.

The circuit of FIG. 4 comprises three P-channel MOS transistors P1, P2,P3 acting as controlled switches. The first two, P1 and P2, have theirmain conduction paths connected in series between a node to be connectedto a program voltage reference VPP and an internal node NN. Thetransistor P3 has its main conduction path connected between a node tobe connected to a boosted voltage reference VEE and the internal nodeNN. The transistors P1 and P2 are input, to their control terminals, twowrite enable signals WE1 and WE2, respectively, which are synchronouswith each other. The transistor P3 is input, to its control terminal, aread enable signal RE. The two transistors in series in the write legserve to prevent spurious current flows between the references VEE andVPP.

The circuit of FIG. 4 further includes a conventional charge pumpcircuit CHP being input a supply voltage VCC and outputting the boostedvoltage VEE. In general, such charge pump circuits include regulatingarrangements to prevent the output voltage from overtaking predeterminedlimits. The output of the circuit CHP is connected to a first terminalof a zener diode DZ acting as a reference voltage generating circuit;the other terminal of the diode DZ is connected to ground, GND.

The output of the circuit CHP is connected to a first end terminal of avoltage divider comprised of four resistors R1, R2, R3, R4 connectedserially together, the second end terminal being connected to ground atGND.

The center taps and first end terminal of the divider are connected tothe non-inverting input of an operational amplifier OA1 via fourcontrolled switches SW1, SW2, SW3, SW4, respectively. In one embodiment,the voltage at the first end terminal, and therefore, the zener voltage,is 12 volts, and the voltages at the center taps are 10, 8 and 7 volts,respectively. The 7-volt voltage is used for reading, and the otherthree for programming three different levels of the threshold voltage.The fourth level is provided by the erasing through exposure to UVradiation.

The amplifier OA1 and a transistor MR1 form the essentials of a voltageregulator of the linear type. The gate terminal of the regulationtransistor MR1 is controlled by the output from the amplifier OA1. Thesource terminal of the transistor MR1 is connected to the invertinginput of the amplifier OA1, and its drain terminal is connected to thenode NN. The output of the linear regulator is the source terminal ofthe transistor MR1.

The circuit of FIG. 5 is basically identical with the circuit of FIG. 4,except that its reference circuit is different and comprises aconventional band-gap circuit BGR being supplied the voltage VCC. Thiscircuit can output a truly stable voltage, typically of 2 volts.

The output of the circuit BGR is connected to the non-inverting input ofanother operational amplifier OA2. The output of the amplifier OA2 isconnected to the gate terminal of another regulation transistor MR2. Themain conduction path of the transistor MR2 is interposed between theoutput of the circuit CHP and the divider input, i.e. the first endterminal thereof. The divider of FIG. 5 has four center taps, becauseone of these, presenting a corresponding voltage to that from thecircuit BGR, is to be connected to the inverting input of the amplifierOA2.

The operation of the circuits shown in FIGS. 4 and 5 is substantiallythe same.

The transistors P1, P2, P3 function to select the supply source from VPPor VEE, while preventing spurious current flows from occurring betweenthe two sources.

The transistor MR1, in cooperation with the amplifier OA1, sets thevoltage VW to the voltage value present at the amplifier non-invertingterminal, i.e. the voltage value of the tap selected by means of theswitches SW1, . . . , SW4.

The voltage at the divider input corresponds to the voltage from thecircuit CHP as stabilized by a suitable stabilizing circuit comprised ofthe zener diode DZ of FIG. 4, the band-gap circuit BGR jointly with theamplifier OA2, and the transistor MR2 of FIG. 5.

What is claimed is:
 1. A multi-level memory circuit comprising:aplurality of memory cells, each for storing more than one item of binaryinformation and comprising at least one floating gate MOS transistor,the information stored in each cell corresponding to a threshold voltagelevel thereof; and a write signal generating circuit for said pluralityof memory cells and having an input connected to a supply voltage, saidwrite signal generating circuit generating internally a write signalvoltage having a selectable value from a number of regulated discretespaced apart voltage values corresponding to a number of discrete spacedapart threshold voltage levels wherein said write signal generatingcircuit comprises at least one linear voltage regulating circuitincluding a reference circuit for generating a stable reference voltage.2. A multi-level memory circuit according to claim 1, wherein saidregulating circuit includes a voltage divider connected to the output ofsaid reference circuit and having a plurality of taps for providing acorresponding plurality of discrete spaced apart reference voltages. 3.A multi-level memory circuit according to claim 1, wherein said writesignal generating circuit comprises:a voltage booster circuit forgenerating a higher voltage output than the supply voltage; and at leastone voltage regulating circuit connected to the output of said boostercircuit.
 4. A multi-level memory circuit according to claim 1, whereinsaid write signal generating circuit generates a single write signalvoltage pulse for each write operation into a cell, an amplitude of thesingle write signal voltage pulse corresponding to a write signalvoltage value associated with information to be stored.
 5. A multi-levelmemory circuit according to claim 4, wherein said write signalgenerating circuit also controls a duration of the single write signalvoltage pulse.
 6. A multi-level memory circuit according to claim 1,wherein the discrete spaced apart threshold voltage levels are four innumber.
 7. A multi-level memory circuit according to claim 1, whereineach of said plurality of memory cells is an EPROM cell.
 8. Amulti-level memory circuit according to claim 1, wherein each of saidplurality of memory cells is an OTP cell.
 9. A multi-level memorycircuit comprising:a plurality of memory cells, each for storing morethan one item of binary information and comprising at least one floatinggate MOS transistor, the information stored in each cell correspondingto a threshold voltage level thereof; and a write signal generatingcircuit for said plurality of memory cells generating internally anumber of regulated discrete spaced apart write signal voltagescorresponding to a number of discrete spaced apart threshold voltagelevels wherein said write signal generating circuit comprises at leastone linear voltage regulating circuit including a reference circuit forgenerating a stable reference voltage.
 10. A multi-level memory circuitaccording to claim 9, wherein said write signal generating circuit hasan input connected to a supply voltage, and wherein at least one of theregulated discrete spaced apart write signal voltages is greater thanthe supply voltage.
 11. A multi-level memory circuit according to claim9, wherein said regulating circuit includes a voltage divider connectedto the output of said reference circuit and having a plurality of tapsfor providing a corresponding plurality of discrete spaced apartreference voltages.
 12. A multi-level memory circuit according to claim9, wherein said write signal generating circuit comprises:a voltagebooster circuit for generating a higher voltage output than the supplyvoltage; and at least one voltage regulating circuit connected to theoutput of said booster circuit.
 13. A multi-level memory circuitaccording to claim 9, wherein said write signal generating circuitgenerates a single write signal voltage pulse for each write operationinto a cell, an amplitude of the single write signal voltage pulsecorresponding to a write signal voltage value associated withinformation to be stored.
 14. A multi-level memory circuit according toclaim 13, wherein said write signal generating circuit also controls aduration of the single write signal voltage pulse.
 15. A multi-levelmemory circuit according to claim 9, wherein the discrete spaced apartthreshold voltage levels are four in number.
 16. A multi-level memorycircuit according to claim 9, wherein each of said plurality of memorycells is an EPROM cell.
 17. A multi-level memory circuit according toclaim 9, wherein each of said plurality of memory cells is an OTP cell.18. A semiconductor integrated electronic storage device comprising:atleast one memory circuit comprisinga plurality of memory cells, each forstoring more than one item of binary information and comprising at leastone floating gate MOS transistor, the information stored in each cellcorresponding to a threshold voltage level thereof, and a write signalgenerating circuit for said plurality of memory cells generatinginternally a number of regulated discrete spaced apart write voltagescorresponding to a number of discrete spaced apart threshold voltagelevels wherein said write signal generating circuit comprises at leastone linear voltage regulating circuit including a reference circuit forgenerating a stable reference voltage.
 19. A semiconductor integratedelectronic storage device according to claim 18, wherein said writesignal generating circuit has an input connected to a supply voltage,and wherein at least one of the regulated discrete spaced apart writesignal voltages is greater than the supply voltage.
 20. A semiconductorintegrated electronic storage device according to claim 18, wherein saidregulating circuit includes a voltage divider connected to the output ofsaid reference circuit and having a plurality of taps for providing acorresponding plurality of discrete spaced apart reference voltages. 21.A semiconductor integrated electronic storage device according to claim18, wherein said write signal generating circuit comprises:a voltagebooster circuit for generating a higher voltage output than the supplyvoltage; and at least one voltage regulating circuit connected to theoutput of said booster circuit.
 22. A semiconductor integratedelectronic storage device according to claim 18, wherein said writesignal generating circuit generates a single write signal voltage pulsefor each write operation into a cell, an amplitude of the single writesignal voltage pulse corresponding to a write signal voltage valueassociated with information to be stored.
 23. A semiconductor integratedelectronic storage device according to claim 22, wherein said writesignal generating circuit also controls a duration of the single writesignal voltage pulse.
 24. A semiconductor integrated electronic storagedevice according to claim 18, wherein the discrete spaced apartthreshold voltage levels are four in number.
 25. A semiconductorintegrated electronic storage device according to claim 18, wherein eachof said plurality of memory cells is an EPROM cell.
 26. A semiconductorintegrated electronic storage device according to claim 18, wherein eachof said plurality of memory cells is an OTP cell.
 27. A semiconductorintegrated electronic storage device according to claim 18 furthercomprising at least one logic circuit connected to the at least onememory circuit for one of reading and writing information.